ID
string | Name
string | Abstraction
string | Structure
string | Status
string | Description
string | ExtendedDescription
string | ApplicablePlatforms
list | AlternateTerms
list | ModesOfIntroduction
list | CommonConsequences
list | PotentialMitigations
list | ObservedExamples
list | AffectedResources
sequence | TaxonomyMappings
list | RelatedAttackPatterns
sequence | References
list | Notes
list | ContentHistory
list | MappingNotes_Usage
string | MappingNotes_Rationale
string | MappingNotes_Comments
string | MappingNotes_Reasons
sequence | MappingNotes_Suggestions
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list | WeaknessOrdinalities
list | DetectionMethods
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list | FunctionalAreas
sequence | Diagram
string | LikelihoodOfExploit
string | BackgroundDetails
sequence | NumPaths
int64 | Paths
sequence | Children
sequence |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
284
|
Improper Access Control
|
Pillar
|
Simple
|
Incomplete
|
The product does not restrict or incorrectly restricts access to a resource from an unauthorized actor.
|
Access control involves the use of several protection mechanisms such as:
- Authentication (proving the identity of an actor)
- Authorization (ensuring that a given actor can access a resource), and
- Accountability (tracking of activities that were performed)
When any mechanism is not applied or otherwise fails, attackers can compromise the security of the product by gaining privileges, reading sensitive information, executing commands, evading detection, etc.
There are two distinct behaviors that can introduce access control weaknesses:
- Specification: incorrect privileges, permissions, ownership, etc. are explicitly specified for either the user or the resource (for example, setting a password file to be world-writable, or giving administrator capabilities to a guest user). This action could be performed by the program or the administrator.
- Enforcement: the mechanism contains errors that prevent it from properly enforcing the specified access control requirements (e.g., allowing the user to specify their own privileges, or allowing a syntactically-incorrect ACL to produce insecure settings). This problem occurs within the program itself, in that it does not actually enforce the intended security policy that the administrator specifies.
|
[
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": "ICS/OT",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] |
[
{
"Description": "The terms \"access control\" and \"authorization\" are often used interchangeably, although many people have distinct definitions. The CWE usage of \"access control\" is intended as a general term for the various mechanisms that restrict which users can access which resources, and \"authorization\" is more narrowly defined. It is unlikely that there will be community consensus on the use of these terms.",
"Term": "Authorization"
}
] |
[
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": "REALIZATION: This weakness is caused during implementation of an architectural security tactic.",
"Phase": "Implementation"
},
{
"Note": null,
"Phase": "Operation"
}
] |
[
{
"Impact": [
"Varies by Context"
],
"Likelihood": null,
"Note": null,
"Scope": [
"Other"
]
}
] |
[
{
"Description": "Very carefully manage the setting, management, and handling of privileges. Explicitly manage trust zones in the software.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": "MIT-1",
"Phase": [
"Architecture and Design",
"Operation"
],
"Strategy": null
},
{
"Description": "\n\nCompartmentalize the system to have \"safe\" areas where trust boundaries can be unambiguously drawn. Do not allow sensitive data to go outside of the trust boundary and always be careful when interfacing with a compartment outside of the safe area.\n\n\nEnsure that appropriate compartmentalization is built into the system design, and the compartmentalization allows for and reinforces privilege separation functionality. Architects and designers should rely on the principle of least privilege to decide the appropriate time to use privileges and the time to drop privileges.\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": "MIT-46",
"Phase": [
"Architecture and Design"
],
"Strategy": "Separation of Privilege"
}
] |
[
{
"Description": "A form hosting website only checks the session authentication status for a single form, making it possible to bypass authentication when there are multiple forms",
"Link": "https://www.cve.org/CVERecord?id=CVE-2022-24985",
"Reference": "CVE-2022-24985"
},
{
"Description": "Access-control setting in web-based document collaboration tool is not properly implemented by the code, which prevents listing hidden directories but does not prevent direct requests to files in those directories.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2022-29238",
"Reference": "CVE-2022-29238"
},
{
"Description": "Python-based HTTP library did not scope cookies to a particular domain such that \"supercookies\" could be sent to any domain on redirect",
"Link": "https://www.cve.org/CVERecord?id=CVE-2022-23607",
"Reference": "CVE-2022-23607"
},
{
"Description": "Chain: Cloud computing virtualization platform does not require authentication for upload of a tar format file (CWE-306), then uses .. path traversal sequences (CWE-23) in the file to access unexpected files, as exploited in the wild per CISA KEV.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2021-21972",
"Reference": "CVE-2021-21972"
},
{
"Description": "IT management product does not perform authentication for some REST API requests, as exploited in the wild per CISA KEV.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2021-37415",
"Reference": "CVE-2021-37415"
},
{
"Description": "Firmware for a WiFi router uses a hard-coded password for a BusyBox shell, allowing bypass of authentication through the UART port",
"Link": "https://www.cve.org/CVERecord?id=CVE-2021-35033",
"Reference": "CVE-2021-35033"
},
{
"Description": "Bluetooth speaker does not require authentication for the debug functionality on the UART port, allowing root shell access",
"Link": "https://www.cve.org/CVERecord?id=CVE-2020-10263",
"Reference": "CVE-2020-10263"
},
{
"Description": "Default setting in workflow management product allows all API requests without authentication, as exploited in the wild per CISA KEV.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2020-13927",
"Reference": "CVE-2020-13927"
},
{
"Description": "Bulletin board applies restrictions on number of images during post creation, but does not enforce this on editing.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2010-4624",
"Reference": "CVE-2010-4624"
}
] |
[
"File or Directory"
] |
[
{
"EntryID": null,
"EntryName": "Access Control List (ACL) errors",
"MappingFit": null,
"TaxonomyName": "PLOVER"
},
{
"EntryID": "2",
"EntryName": "Insufficient Authorization",
"MappingFit": null,
"TaxonomyName": "WASC"
},
{
"EntryID": null,
"EntryName": "Missing Access Control",
"MappingFit": null,
"TaxonomyName": "7 Pernicious Kingdoms"
}
] |
[
"19",
"441",
"478",
"479",
"502",
"503",
"536",
"546",
"550",
"551",
"552",
"556",
"558",
"562",
"563",
"564",
"578"
] |
[
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"Michael Howard",
"David LeBlanc"
],
"Edition": "2nd Edition",
"ExternalReferenceID": "REF-7",
"Publication": null,
"PublicationDay": "04",
"PublicationMonth": "12",
"PublicationYear": "2002",
"Publisher": "Microsoft Press",
"Section": "Chapter 6, \"Determining Appropriate Access Control\" Page 171",
"Title": "Writing Secure Code",
"URL": "https://www.microsoftpressstore.com/store/writing-secure-code-9780735617223",
"URLDate": null
},
{
"Authors": [
"Michael Howard",
"David LeBlanc",
"John Viega"
],
"Edition": null,
"ExternalReferenceID": "REF-44",
"Publication": "McGraw-Hill",
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": "2010",
"Publisher": null,
"Section": "\"Sin 17: Failure to Protect Stored Data.\" Page 253",
"Title": "24 Deadly Sins of Software Security",
"URL": null,
"URLDate": null
},
{
"Authors": [
"MITRE"
],
"Edition": null,
"ExternalReferenceID": "REF-1287",
"Publication": null,
"PublicationDay": "28",
"PublicationMonth": "06",
"PublicationYear": "2022",
"Publisher": null,
"Section": "Details of Problematic Mappings",
"Title": "Supplemental Details - 2022 CWE Top 25",
"URL": "https://cwe.mitre.org/top25/archive/2022/2022_cwe_top25_supplemental.html#problematicMappingDetails",
"URLDate": "2024-11-17"
}
] |
[
{
"Note": "\n\nThis entry needs more work. Possible sub-categories include:\n\n\n - Trusted group includes undesired entities (partially covered by CWE-286)\n\n - Group can perform undesired actions\n\n - ACL parse error does not fail closed\n\n",
"Type": "Maintenance"
}
] |
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Discouraged
|
CWE-284 is extremely high-level, a Pillar. Its name, "Improper Access Control," is often misused in low-information vulnerability reports [REF-1287] or by active use of the OWASP Top Ten, such as "A01:2021-Broken Access Control". It is not useful for trend analysis.
|
Consider using descendants of CWE-284 that are more specific to the kind of access control involved, such as those involving authorization (Missing Authorization (CWE-862), Incorrect Authorization (CWE-863), Incorrect Permission Assignment for Critical Resource (CWE-732), etc.); authentication (Missing Authentication (CWE-306) or Weak Authentication (CWE-1390)); Incorrect User Management (CWE-286); Improper Restriction of Communication Channel to Intended Endpoints (CWE-923); etc.
|
[
"Frequent Misuse",
"Abstraction"
] |
[
{
"Comment": "Missing Authorization",
"CweID": "862"
},
{
"Comment": "Incorrect Authorization",
"CweID": "863"
},
{
"Comment": "Incorrect Permission Assignment for Critical Resource",
"CweID": "732"
},
{
"Comment": "Missing Authentication",
"CweID": "306"
},
{
"Comment": "Weak Authentication",
"CweID": "1390"
},
{
"Comment": "Improper Restriction of Communication Channel to Intended Endpoints",
"CweID": "923"
}
] |
[] | null | null | null | null | null | null | null | 1
|
[
[
"284"
]
] |
[
"1191",
"1220",
"1224",
"1231",
"1233",
"1242",
"1252",
"1257",
"1259",
"1260",
"1262",
"1263",
"1267",
"1268",
"1270",
"1274",
"1276",
"1280",
"1283",
"1290",
"1292",
"1294",
"1296",
"1304",
"1311",
"1312",
"1313",
"1315",
"1316",
"1317",
"1320",
"1323",
"1334",
"269",
"282",
"285",
"286",
"287",
"346",
"749",
"923"
] |
1191
|
On-Chip Debug and Test Interface With Improper Access Control
|
Base
|
Simple
|
Stable
|
The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
|
A device's internal information may be accessed through a scan chain of interconnected internal registers, usually through a JTAG interface. The JTAG interface provides access to these registers in a serial fashion in the form of a scan chain for the purposes of debugging programs running on a device. Since almost all information contained within a device may be accessed over this interface, device manufacturers typically insert some form of authentication and authorization to prevent unintended use of this sensitive information. This mechanism is implemented in addition to on-chip protections that are already present.
If authorization, authentication, or some other form of access control is not implemented or not implemented correctly, a user may be able to bypass on-chip protection mechanisms through the debug interface.
Sometimes, designers choose not to expose the debug pins on the motherboard. Instead, they choose to hide these pins in the intermediate layers of the board. This is primarily done to work around the lack of debug authorization inside the chip. In such a scenario (without debug authorization), when the debug interface is exposed, chip internals are accessible to an attacker.
|
[
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
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"Name": null,
"Prevalence": "Undetermined",
"Type": "Architecture"
},
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
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[
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": null,
"Phase": "Implementation"
}
] |
[
{
"Impact": [
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],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality"
]
},
{
"Impact": [
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],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality"
]
},
{
"Impact": [
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],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Authorization"
]
},
{
"Impact": [
"Modify Memory"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Integrity"
]
},
{
"Impact": [
"Modify Application Data"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Integrity"
]
},
{
"Impact": [
"Bypass Protection Mechanism"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Access Control"
]
}
] |
[
{
"Description": "If feasible, the manufacturer should disable the JTAG interface or implement authentication and authorization for the JTAG interface. If authentication logic is added, it should be resistant to timing attacks. Security-sensitive data stored in registers, such as keys, etc. should be cleared when entering debug mode.",
"Effectiveness": "High",
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design"
],
"Strategy": "Separation of Privilege"
}
] |
[
{
"Description": "chain: JTAG interface is not disabled (CWE-1191) during ROM code execution, introducing a race condition (CWE-362) to extract encryption keys",
"Link": "https://www.cve.org/CVERecord?id=CVE-2019-18827",
"Reference": "CVE-2019-18827"
}
] | null | null |
[
"1",
"180"
] |
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"Ramesh Karri"
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"ExternalReferenceID": "REF-1037",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": "02",
"PublicationYear": "2010",
"Publisher": null,
"Section": null,
"Title": "Attacks and Defenses for JTAG",
"URL": "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5406671",
"URLDate": null
},
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"Wonjun Lee"
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"ExternalReferenceID": "REF-1043",
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"PublicationDay": "03",
"PublicationMonth": "12",
"PublicationYear": "2018",
"Publisher": null,
"Section": null,
"Title": "Exploiting JTAG and Its Mitigation in IOT: A Survey",
"URL": "https://www.mdpi.com/1999-5903/10/12/121/pdf",
"URLDate": "2023-04-07"
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"URLDate": "2023-04-07"
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{
"Note": "CWE-1191 and CWE-1244 both involve physical debug access, but the weaknesses are different. CWE-1191 is effectively about missing authorization for a debug interface, i.e. JTAG. CWE-1244 is about providing internal assets with the wrong debug access level, exposing the asset to untrusted debug agents.",
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] |
Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] |
[
{
"Description": null,
"Ordinality": "Primary"
}
] |
[
{
"Description": "\n\nAuthentication and authorization of debug and test interfaces should be part of the architecture and design review process. Withholding of private register documentation from the debug and test interface public specification (\"Security by obscurity\") should not be considered as sufficient security.\n",
"DetectionMethodID": null,
"Effectiveness": null,
"EffectivenessNotes": null,
"Method": "Dynamic Analysis with Manual Results Interpretation"
},
{
"Description": "\n\nDynamic tests should be done in the pre-silicon and post-silicon stages to verify that the debug and test interfaces are not open by default.\n",
"DetectionMethodID": null,
"Effectiveness": null,
"EffectivenessNotes": null,
"Method": "Dynamic Analysis with Manual Results Interpretation"
},
{
"Description": "Tests that fuzz Debug and Test Interfaces should ensure that no access without appropriate authentication and authorization is possible.",
"DetectionMethodID": null,
"Effectiveness": "Moderate",
"EffectivenessNotes": null,
"Method": "Fuzzing"
}
] |
[
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "A home, WiFi-router device implements a login prompt which prevents an unauthorized user from issuing any commands on the device until appropriate credentials are provided. The credentials are protected on the device and are checked for strength against attack.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "If the JTAG interface on this device is not hidden by the manufacturer, the interface may be identified using tools such as JTAGulator. If it is hidden but not disabled, it can be exposed by physically wiring to the board.\n\n\nBy issuing a \"halt\" command before the OS starts, the unauthorized user pauses the watchdog timer and prevents the router from restarting (once the watchdog timer would have expired). Having paused the router, an unauthorized user is able to execute code and inspect and modify data in the device, even extracting all of the router's firmware. This allows the user to examine the router and potentially exploit it.",
"IntroText": null,
"Language": "Other",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "JTAG is useful to chip and device manufacturers during design, testing, and production and is included in nearly every product. Without proper authentication and authorization, the interface may allow tampering with a product.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
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},
{
"BodyText": null,
"ExampleCode": "In order to prevent exposing the debugging interface, manufacturers might try to obfuscate the JTAG interface or blow device internal fuses to disable the JTAG interface. Adding authentication and authorization to this interface makes use by unauthorized individuals much more difficult.",
"IntroText": null,
"Language": "Other",
"Nature": "Good",
"Reference": null
}
],
"ID": null
},
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "The following example code is a snippet from the JTAG wrapper module in the RISC-V debug module of the HACK@DAC'21 Openpiton SoC [REF-1355]. To make sure that the JTAG is accessed securely, the developers have included a primary authentication mechanism based on a password.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "The developers employed a Finite State Machine (FSM) to implement this authentication. When a user intends to read from or write to the JTAG module, they must input a password.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "In the subsequent state of the FSM module, the entered password undergoes Hash-based Message Authentication Code (HMAC) calculation using an internal HMAC submodule. Once the HMAC for the entered password is computed by the HMAC submodule, the FSM transitions to the next state, where it compares the computed HMAC with the expected HMAC for the password.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "If the computed HMAC matches the expected HMAC, the FSM grants the user permission to perform read or write operations on the JTAG module. [REF-1352]",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "```\n\t...\n\t\tPassChkValid: begin\n\t\t\tif(hashValid) begin\n```\nif(exp_hash == pass_hash) begin** \n\t\t\t\t\n\t\t\t\t```\n```\npass_check = 1'b1;** \n\t\t\t\t **end else begin** \n\t\t\t\t```\n```\npass_check = 1'b0;** \n\t\t\t\t **end\n\t\t\t\t\t state_d = Idle;** end else begin \n\t\t\t```\n\t\t\t\tstate_d = PassChkValid;\n\t\t\t end\n\t\t end\n\t ...\n```",
"IntroText": null,
"Language": "Verilog",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "However, in the given vulnerable part of the code, the JTAG module has not defined a limitation for several continuous wrong password attempts. This omission poses a significant security risk, allowing attackers to carry out brute-force attacks without restrictions.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "Without a limitation on wrong password attempts, an attacker can repeatedly guess different passwords until they gain unauthorized access to the JTAG module. This leads to various malicious activities, such as unauthorized read from or write to debug module interface.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "To mitigate the mentioned vulnerability, developers need to implement a restriction on the number of consecutive incorrect password attempts allowed by the JTAG module, which can achieve by incorporating a mechanism that temporarily locks the module after a certain number of failed attempts.[REF-1353][REF-1354]",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
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},
{
"BodyText": null,
"ExampleCode": "```\n\t...\n\t case (state_q) \n\t\tIdle: begin\n\t\t ... \n\t\t\telse if ( (dm::dtm_op_e'(dmi.op) == dm::DTM_PASS) && \n```\n(miss_pass_check_cnt_q != 2'b11)** )\n\t\t\t begin \n\t\t\t```\n\t\t\t\tstate_d = Write;\n\t\t\t\tpass_mode = 1'b1;\n\t\t\t end\n\t\t ...\n\t\t end\n\t\t ...\n\t\tPassChkValid: begin\n\t\t\tif(hashValid) begin\n\t\t\t\tif(exp_hash == pass_hash) begin\n\t\t\t\t\tpass_check = 1'b1;\n\t\t\t\t end else begin \n\t\t\t\t\tpass_check = 1'b0;\n```\nmiss_pass_check_cnt_d = miss_pass_check_cnt_q + 1** end\n\t\t\t\t state_d = Idle; end else begin \n\t\t\t```\n\t\t\t\tstate_d = PassChkValid;\n\t\t\t end\n\t\t end\n\t ...\n```",
"IntroText": null,
"Language": "Verilog",
"Nature": "Good",
"Reference": null
}
],
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},
{
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{
"BodyText": null,
"ExampleCode": null,
"IntroText": "The example code below is taken from the JTAG access control mechanism of the HACK@DAC'21 buggy OpenPiton SoC [REF-1364]. Access to JTAG allows users to access sensitive information in the system. Hence, access to JTAG is controlled using cryptographic authentication of the users. In this example (see the vulnerable code source), the password checker uses HMAC-SHA256 for authentication. It takes a 512-bit secret message from the user, hashes it using HMAC, and compares its output with the expected output to determine the authenticity of the user.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "...\n\n **logic [31-1:0] data_d,** data_q;\n ...\n\n **logic [512-1:0] pass_data;** \n ...\n\n```\n\t Write: begin\n\t\t ...\n\t\t\t if (pass_mode) begin\n```\npass_data = { {60{8'h00}}, data_d};** \n\t\t\t\t state_d = PassChk;\n\t\t\t\t pass_mode = 1'b0;\n\t\t\t\t ...\n\t\t\t end\n\t ...",
"IntroText": null,
"Language": "Verilog",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "The vulnerable code shows an incorrect implementation of the HMAC authentication where it only uses the least significant 32 bits of the secret message for the authentication (the remaining 480 bits are hard coded as zeros). As a result, the system is susceptible to brute-force attacks on the access control mechanism of JTAG, where the attacker only needs to determine 32 bits of the secret message instead of 512 bits.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "To mitigate this issue, remove the zero padding and use all 512 bits of the secret message for HMAC authentication [REF-1365].",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "...\n\n **logic [512-1:0] data_d,** data_q;\n ...\n logic [512-1:0] pass_data;\n ...\n\n```\n\t Write: begin\n\t\t ...\n\t\t\t if (pass_mode) begin\n```\npass_data = data_d;** \n\t\t\t\t state_d = PassChk;\n\t\t\t\t pass_mode = 1'b0;\n\t\t\t\t ...\n\t\t\t end\n\t ...",
"IntroText": null,
"Language": "Verilog",
"Nature": "Good",
"Reference": null
}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1191"
]
] |
[] |
1220
|
Insufficient Granularity of Access Control
|
Base
|
Simple
|
Incomplete
|
The product implements access controls via a policy or other feature with the intention to disable or restrict accesses (reads and/or writes) to assets in a system from untrusted agents. However, implemented access controls lack required granularity, which renders the control policy too broad because it allows accesses from unauthorized agents to the security-sensitive assets.
|
Integrated circuits and hardware engines can expose accesses to assets (device configuration, keys, etc.) to trusted firmware or a software module (commonly set by BIOS/bootloader). This access is typically access-controlled. Upon a power reset, the hardware or system usually starts with default values in registers, and the trusted firmware (Boot firmware) configures the necessary access-control protection.
A common weakness that can exist in such protection schemes is that access controls or policies are not granular enough. This condition allows agents beyond trusted agents to access assets and could lead to a loss of functionality or the ability to set up the device securely. This further results in security risks from leaked, sensitive, key material to modification of device configuration.
|
[
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Architecture"
},
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": "Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during hardware implementation and identified later during Testing or System Configuration phases.",
"Phase": "Implementation"
}
] |
[
{
"Impact": [
"Modify Memory",
"Read Memory",
"Execute Unauthorized Code or Commands",
"Gain Privileges or Assume Identity",
"Bypass Protection Mechanism",
"Other"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality",
"Integrity",
"Availability",
"Access Control"
]
}
] |
[
{
"Description": "\n\n - Access-control-policy protections must be reviewed for design inconsistency and common weaknesses.\n\n - Access-control-policy definition and programming flow must be tested in pre-silicon, post-silicon testing.\n\n",
"Effectiveness": "High",
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design",
"Implementation",
"Testing"
],
"Strategy": null
}
] |
[
{
"Description": "A form hosting website only checks the session authentication status for a single form, making it possible to bypass authentication when there are multiple forms",
"Link": "https://www.cve.org/CVERecord?id=CVE-2022-24985",
"Reference": "CVE-2022-24985"
},
{
"Description": "An operating system has an overly permission Access Control List onsome system files, including those related to user passwords",
"Link": "https://www.cve.org/CVERecord?id=CVE-2021-36934",
"Reference": "CVE-2021-36934"
}
] | null | null |
[
"1",
"180"
] |
[
{
"Authors": null,
"Edition": null,
"ExternalReferenceID": "REF-1346",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": "2019",
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"Section": null,
"Title": "axi_node_intf_wrap.sv",
"URL": "https://github.com/HACK-EVENT/hackatdac19/blob/619e9fb0ef32ee1e01ad76b8732a156572c65700/src/axi_node/src/axi_node_intf_wrap.sv#L430",
"URLDate": "2023-09-18"
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"Title": "axi_node_intf_wrap.sv",
"URL": "https://github.com/HACK-EVENT/hackatdac19/blob/2078f2552194eda37ba87e54cbfef10f1aa41fa5/src/axi_node/src/axi_node_intf_wrap.sv#L430",
"URLDate": "2023-09-18"
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] |
Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null |
[
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "Consider a system with a register for storing AES key for encryption or decryption. The key is 128 bits, implemented as a set of four 32-bit registers. The key registers are assets and registers, AES_KEY_READ_POLICY and AES_KEY_WRITE_POLICY, and are defined to provide necessary access controls.\n\n\nThe read-policy register defines which agents can read the AES-key registers, and write-policy register defines which agents can program or write to those registers. Each register is a 32-bit register, and it can support access control for a maximum of 32 agents. The number of the bit when set (i.e., \"1\") allows respective action from an agent whose identity matches the number of the bit and, if \"0\" (i.e., Clear), disallows the respective action to that corresponding agent.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "| Register | Field description | \n| --- | --- |\n| AES_ENC_DEC_KEY_0 | AES key [0:31] for encryption or decryption Default 0x00000000 |\n| AES_ENC_DEC_KEY_1 | AES key [32:63] for encryption or decryption Default 0x00000000 |\n| AES_ENC_DEC_KEY_2 | AES key [64:95] for encryption or decryption Default 0x00000000 |\n| AES_ENC_DEC_KEY_4 | AES key [96:127] for encryption or decryption Default 0x00000000 |\n| AES_KEY_READ_WRITE_POLICY | [31:0] Default 0x00000006 - meaning agent with identities \"1\" and \"2\" can both read from and write to key registers |",
"IntroText": null,
"Language": "Other",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "In the above example, there is only one policy register that controls access to both read and write accesses to the AES-key registers, and thus the design is not granular enough to separate read and writes access for different agents. Here, agent with identities \"1\" and \"2\" can both read and write.",
"ExampleCode": null,
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},
{
"BodyText": "A good design should be granular enough to provide separate access controls to separate actions. Access control for reads should be separate from writes. Below is an example of such implementation where two policy registers are defined for each of these actions. The policy is defined such that: the AES-key registers can only be read or used by a crypto agent with identity \"1\" when bit #1 is set. The AES-key registers can only be programmed by a trusted firmware with identity \"2\" when bit #2 is set.",
"ExampleCode": null,
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},
{
"BodyText": null,
"ExampleCode": "| | \n|\n| AES_KEY_READ_POLICY | [31:0] Default 0x00000002 - meaning only Crypto engine with identity \"1\" can read registers: AES_ENC_DEC_KEY_0, AES_ENC_DEC_KEY_1, AES_ENC_DEC_KEY_2, AES_ENC_DEC_KEY_3 |\n| AES_KEY_WRITE_POLICY | [31:0] Default 0x00000004 - meaning only trusted firmware with identity \"2\" can program registers: AES_ENC_DEC_KEY_0, AES_ENC_DEC_KEY_1, AES_ENC_DEC_KEY_2, AES_ENC_DEC_KEY_3 |",
"IntroText": null,
"Language": null,
"Nature": "Good",
"Reference": null
}
],
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},
{
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{
"BodyText": null,
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"IntroText": "Within the AXI node interface wrapper module in the RISC-V AXI module of the HACK@DAC'19 CVA6 SoC [REF-1346], an access control mechanism is employed to regulate the access of different privileged users to peripherals.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "The AXI ensures that only users with appropriate privileges can access specific peripherals. For instance, a ROM module is accessible exclusively with Machine privilege, and AXI enforces that users attempting to read data from the ROM must possess machine privilege; otherwise, access to the ROM is denied. The access control information and configurations are stored in a ROM.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "```\n\t...\n\t\tfor (i=0; i<NB_SUBORDINATE; i++)\n\t\t begin \n\t\t\tfor (j=0; j<NB_MANAGER; j++)\n\t\t\t begin \n```\nassign connectivity_map_o[i][j] = access_ctrl_i[i][j][priv_lvl_i] || ((j==6) && access_ctrl_i[i][7][priv_lvl_i]);** end end ...",
"IntroText": null,
"Language": "Verilog",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "However, in the example code above, while assigning distinct privileges to AXI manager and subordinates, both the Platform-Level Interrupt Controller Specification (PLIC) and the Core-local Interrupt Controller (CLINT) (which are peripheral numbers 6 and 7 respectively) utilize the same access control configuration. This common configuration diminishes the granularity of the AXI access control mechanism.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "In certain situations, it might be necessary to grant higher privileges for accessing the PLIC than those required for accessing the CLINT. Unfortunately, this differentiation is overlooked, allowing an attacker to access the PLIC with lower privileges than intended.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "As a consequence, unprivileged code can read and write to the PLIC even when it was not intended to do so. In the worst-case scenario, the attacker could manipulate interrupt priorities, potentially modifying the system's behavior or availability.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "To address the aforementioned vulnerability, developers must enhance the AXI access control granularity by implementing distinct access control entries for the Platform-Level Interrupt Controller (PLIC) and the Core-local Interrupt Controller (CLINT). By doing so, different privilege levels can be defined for accessing PLIC and CLINT, effectively thwarting the potential attacks previously highlighted. This approach ensures a more robust and secure system, safeguarding against unauthorized access and manipulation of interrupt priorities. [REF-1347]",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "```\n\t...\n\t\tfor (i=0; i<NB_SUBORDINATE; i++)\n\t\t begin \n\t\t\tfor (j=0; j<NB_MANAGER; j++)\n\t\t\t begin \n```\nassign connectivity_map_o[i][j] = access_ctrl_i[i][j][priv_lvl_i];** end end ...",
"IntroText": null,
"Language": "Verilog",
"Nature": "Good",
"Reference": null
}
],
"ID": null
},
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "Consider the following SoC design. The sram in HRoT has an address range that is readable and writable by unprivileged software and it has an area that is only readable by unprivileged software. The tbus interconnect enforces access control for subordinates on the bus but uses only one bit to control both read and write access. Address 0xA0000000 - 0xA000FFFF is readable and writable by the untrusted cores core{0-N} and address 0xA0010000 - 0xA001FFFF is only readable by the untrusted cores core{0-N}.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "The security policy access control is not granular enough, as it uses one bit to enable both read and write access. This gives write access to an area that should only be readable by unprivileged agents. \n\n\n Access control logic should differentiate between read and write access and to have sufficient address granularity.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1220"
]
] |
[
"1222"
] |
1222
|
Insufficient Granularity of Address Regions Protected by Register Locks
|
Variant
|
Simple
|
Incomplete
|
The product defines a large address region protected from modification by the same register lock control bit. This results in a conflict between the functional requirement that some addresses need to be writable by software during operation and the security requirement that the system configuration lock bit must be set during the boot process.
|
Integrated circuits and hardware IPs can expose the device configuration controls that need to be programmed after device power reset by a trusted firmware or software module (commonly set by BIOS/bootloader) and then locked from any further modification. In hardware design, this is commonly implemented using a programmable lock bit which enables/disables writing to a protected set of registers or address regions. When the programmable lock bit is set, the relevant address region can be implemented as a hardcoded value in hardware logic that cannot be changed later.
A problem can arise wherein the protected region definition is not granular enough. After the programmable lock bit has been set, then this new functionality cannot be implemented without change to the hardware design.
|
[
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Architecture"
},
{
"Class": "System on Chip",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": "Such issues are introduced during hardware architecture and design since software controls and configuration are defined during these phases and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
}
] |
[
{
"Impact": [
"Other"
],
"Likelihood": null,
"Note": "System security configuration cannot be defined in a way that does not conflict with functional requirements of device.",
"Scope": [
"Access Control"
]
}
] |
[
{
"Description": "\n\nThe defining of protected locked registers should be reviewed or tested early in the design phase with software teams to ensure software flows are not blocked by the security locks.\n\n\nAs an alternative to using register lock control bits and fixed access control regions, the hardware design could use programmable security access control configuration so that device trusted firmware can configure and change the protected regions based on software usage and security models.\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design"
],
"Strategy": null
}
] | null | null | null |
[
"679"
] | null | null |
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"SubmissionReleaseDate": "2020-02-24",
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Allowed
|
This CWE entry is at the Variant level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
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"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null |
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{
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"IntroText": "For example, consider a hardware unit with a 32 kilobyte configuration address space where the first 8 kilobyte address contains security sensitive controls that must only be writable by device bootloader. One way to protect the security configuration could be to define a 32 bit system configuration locking register (SYS_LOCK) where each bit lock locks the corresponding 1 kilobyte region.",
"Language": null,
"Nature": null,
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{
"BodyText": null,
"ExampleCode": "| Address | Register | \n| --- | --- |\n| 0x0000 | SYS_LOCK: 32 bit system configuration lock register, each bit is write-1-once |\n| 0x0004 | SECURITY_FEATURE_ENABLE: 32 bit register controlling enabling of security features |\n| ... | |\n| 0x0310 | SW_MODE: 32 bit Software Mode indication register |\n\n\t| Address region | Lock bit | \n| --- | --- |\n| 0x0000 - 0x03FF | SYS_LOCK[0] |\n| 0x0400 - 0x07FF | SYS_LOCK[1] |\n| ... | |\n| 0x7C00 - 0x7FFF | SYS_LOCK[31] |",
"IntroText": null,
"Language": "Other",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "If a register exists within the first kilobyte address range (e.g. SW_MODE, address 0x310) and needs to be software writable at runtime, then this register cannot be written in a securely configured system since SYS_LOCK register lock bit 0 must be set to protect other security settings (e.g. SECURITY_FEATURE_ENABLE, address 0x0004). The only fix would be to change the hardware logic or not set the security lock bit.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
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}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1220",
"1222"
]
] |
[] |
1224
|
Improper Restriction of Write-Once Bit Fields
|
Base
|
Simple
|
Incomplete
|
The hardware design control register "sticky bits" or write-once bit fields are improperly implemented, such that they can be reprogrammed by software.
|
Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to define default values that are hard coded in the hardware description language (HDL) code of the hardware unit. A common security protection method used to protect register settings from modification by software is to make the settings write-once or "sticky." This allows writing to such registers only once, whereupon they become read-only. This is useful to allow initial boot software to configure systems settings to secure values while blocking runtime software from modifying such hardware settings.
Failure to implement write-once restrictions in hardware design can expose such registers to being re-programmed by software and written multiple times. For example, write-once fields could be implemented to only be write-protected if they have been set to value "1", wherein they would work as "write-1-once" and not "write-once".
|
[
{
"Class": null,
"Name": "Verilog",
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": null,
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"Type": "Language"
},
{
"Class": "System on Chip",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.",
"Phase": "Implementation"
}
] |
[
{
"Impact": [
"Varies by Context"
],
"Likelihood": null,
"Note": "System configuration cannot be programmed in a secure way.",
"Scope": [
"Confidentiality",
"Integrity",
"Availability",
"Access Control"
]
}
] |
[
{
"Description": "During hardware design all register write-once or sticky fields must be evaluated for proper configuration.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
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},
{
"Description": "The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
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}
] | null | null | null |
[
"680"
] | null | null |
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Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null |
[
{
"Entries": [
{
"BodyText": null,
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"IntroText": "Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value. This implementation can be for a register that is defined by specification to be a write-once register, since the write_once_status field gets written by input data bit 0 on first write.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "module register_write_once_example\n ( \n input [15:0] Data_in, \n input Clk, \n input ip_resetn, \n input global_resetn,\n input write,\n output reg [15:0] Data_out \n );\n\n reg Write_once_status; \n\n always @(posedge Clk or negedge ip_resetn)\n\n```\n\t if (~ip_resetn)\n\t begin\n\t\t Data_out <= 16'h0000;\n\t\t Write_once_status <= 1'b0; \n\t end \n\t else if (write & ~Write_once_status)\n\t begin\n\t\t Data_out <= Data_in & 16'hFFFE;\n\t\t Write_once_status <= Data_in[0]; // Input bit 0 sets Write_once_status\n\t end\n\t else if (~write)\n\t begin \n\t\t Data_out[15:1] <= Data_out[15:1]; \n\t\t Data_out[0] <= Write_once_status; \n\t end \n endmodule\n```",
"IntroText": null,
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"Nature": "Bad",
"Reference": null
},
{
"BodyText": "The above example only locks further writes if write_once_status bit is written to one. So it acts as write_1-Once instead of the write-once attribute.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
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},
{
"BodyText": null,
"ExampleCode": "module register_write_once_example \n ( \n input [15:0] Data_in, \n input Clk, \n input ip_resetn, \n input global_resetn, \n input write, \n output reg [15:0] Data_out \n ); \n\n reg Write_once_status; \n\n always @(posedge Clk or negedge ip_resetn) \n\n```\n\t if (~ip_resetn) \n\t begin \n\t\t Data_out <= 16'h0000; \n\t\t Write_once_status <= 1'b0; \n\t end \n\t else if (write & ~Write_once_status) \n\t begin \n\t\t Data_out <= Data_in & 16'hFFFE; \n\t\t Write_once_status <= 1'b1; // Write once status set on first write, independent of input \n\t end \n\t else if (~write) \n\t begin \n\t\t Data_out[15:1] <= Data_out[15:1]; \n\t\t Data_out[0] <= Write_once_status; \n\t end \n endmodule\n```",
"IntroText": null,
"Language": "Verilog",
"Nature": "Good",
"Reference": null
}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1224"
]
] |
[] |
1231
|
Improper Prevention of Lock Bit Modification
|
Base
|
Simple
|
Stable
|
The product uses a trusted lock bit for restricting access to registers, address regions, or other resources, but the product does not prevent the value of the lock bit from being modified after it has been set.
|
In integrated circuits and hardware intellectual property (IP) cores, device configuration controls are commonly programmed after a device power reset by a trusted firmware or software module (e.g., BIOS/bootloader) and then locked from any further modification.
This behavior is commonly implemented using a trusted lock bit. When set, the lock bit disables writes to a protected set of registers or address regions. Design or coding errors in the implementation of the lock bit protection feature may allow the lock bit to be modified or cleared by software after it has been set. Attackers might be able to unlock the system and features that the bit is intended to protect.
|
[
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
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},
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": "Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during implementation and identified later during Testing or System Configuration phases.",
"Phase": "Implementation"
}
] |
[
{
"Impact": [
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],
"Likelihood": [
"High"
],
"Note": "Registers protected by lock bit can be modified even when lock is set.",
"Scope": [
"Access Control"
]
}
] |
[
{
"Description": "\n\n - Security lock bit protections must be reviewed for design inconsistency and common weaknesses.\n\n - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.\n\n",
"Effectiveness": "High",
"EffectivenessNotes": null,
"MitigationID": null,
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],
"Strategy": null
}
] |
[
{
"Description": "chip reset clears critical read/write lock permissions for RSA function",
"Link": "https://www.cve.org/CVERecord?id=CVE-2017-6283",
"Reference": "CVE-2017-6283"
}
] | null | null |
[
"680"
] |
[
{
"Authors": null,
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"PublicationYear": "2021",
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"Title": "reglk_wrapper.sv",
"URL": "https://github.com/HACK-EVENT/hackatdac21/blob/b9ecdf6068445d76d6bee692d163fededf7a9d9b/piton/design/chip/tile/ariane/src/reglk/reglk_wrapper.sv#L80C1-L80C48",
"URLDate": "2023-09-18"
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] |
Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] |
[
{
"Description": null,
"Ordinality": "Primary"
}
] |
[
{
"Description": "Set the lock bit. Power cycle the device. Attempt to clear the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.",
"DetectionMethodID": null,
"Effectiveness": "High",
"EffectivenessNotes": null,
"Method": "Manual Analysis"
}
] |
[
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by firmware, and then the register needs to be locked (TEMP_SENSOR_LOCK).",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "| Register | Field description | \n| --- | --- |\n| CRITICAL_TEMP_LIMIT | [31:8] Reserved field; Read only; Default 0 [7:0] Critical temp 0-255 Centigrade; Read-write-lock; Default 125 |\n| TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. Slope value used to map sensor reading to degrees Centigrade. |\n| TEMP_SENSOR_LOCK | [31:1] Reserved field; Read only; Default 0 [0] Lock bit, locks CRITICAL_TEMP_LIMIT and TEMP_SENSOR_CALIB registers; Write-1-once; Default 0 |\n| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on critical temperature detection; Read-write; Default 0 |\n| CURRENT_TEMP | [31:8] Reserved field; Read only; Default 0 [7:0] Current Temp 0-255 Centigrade; Read-only; Default 0 |",
"IntroText": null,
"Language": "Other",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "In this example, note that if the system heats to critical temperature, the response of the system is controlled by the TEMP_HW_SHUTDOWN bit [1], which is not lockable. Thus, the intended security property of the critical temperature sensor cannot be fully protected, since software can misconfigure the TEMP_HW_SHUTDOWN register even after the lock bit is set to disable the shutdown response.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "To fix this weakness, one could change the TEMP_HW_SHUTDOWN field to be locked by TEMP_SENSOR_LOCK.\n\n| | \n|\n| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on critical temperature detection; Read-write-Lock; Default 0 [0] Locked by TEMP_SENSOR_LOCK |",
"IntroText": null,
"Language": null,
"Nature": "Good",
"Reference": null
}
],
"ID": null
},
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "The following example code is a snippet from the register locks inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1350]. Register locks help prevent SoC peripherals' registers from malicious use of resources. The registers that can potentially leak secret data are locked by register locks.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "In the vulnerable code, the reglk_mem is used for locking information. If one of its bits toggle to 1, the corresponding peripheral's registers will be locked. In the context of the HACK@DAC System-on-Chip (SoC), it is pertinent to note the existence of two distinct categories of reset signals.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "First, there is a global reset signal denoted as \"rst_ni,\" which possesses the capability to simultaneously reset all peripherals to their respective initial states.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "Second, we have peripheral-specific reset signals, such as \"rst_9,\" which exclusively reset individual peripherals back to their initial states. The administration of these reset signals is the responsibility of the reset controller module.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "```\n\talways @(posedge clk_i)\n\t\tbegin\n```\nif(~(rst_ni && ~jtag_unlock && ~rst_9))** \n\t\t\t\n\t\t\t```\n\t\t\t\tbegin \n\t\t\t\t\tfor (j=0; j < 6; j=j+1) begin \n\t\t\t\t\t\treglk_mem[j] <= 'h0;\n\t\t\t\t end\n\t end\n\t...\n```",
"IntroText": null,
"Language": "Verilog",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "In the buggy SoC architecture during HACK@DAC'21, a critical issue arises within the reset controller module. Specifically, the reset controller can inadvertently transmit a peripheral reset signal to the register lock within the user privilege domain.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "This unintentional action can result in the reset of the register locks, potentially exposing private data from all other peripherals, rendering them accessible and readable.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": "To mitigate the issue, remove the extra reset signal rst_9 from the register lock if condition. [REF-1351]",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "```\n\talways @(posedge clk_i)\n\t\tbegin\n```\nif(~(rst_ni && ~jtag_unlock))** \n\t\t\t\n\t\t\t```\n\t\t\t\tbegin \n\t\t\t\t\tfor (j=0; j < 6; j=j+1) begin \n\t\t\t\t\t\treglk_mem[j] <= 'h0;\n\t\t\t\t end\n\t end\n\t...\n```",
"IntroText": null,
"Language": "Verilog",
"Nature": "Good",
"Reference": null
}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1231"
]
] |
[] |
1233
|
Security-Sensitive Hardware Controls with Missing Lock Bit Protection
|
Base
|
Simple
|
Stable
|
The product uses a register lock bit protection mechanism, but it does not ensure that the lock bit prevents modification of system registers or controls that perform changes to important hardware system configuration.
|
Integrated circuits and hardware intellectual properties (IPs) might provide device configuration controls that need to be programmed after device power reset by a trusted firmware or software module, commonly set by BIOS/bootloader. After reset, there can be an expectation that the controls cannot be used to perform any further modification. This behavior is commonly implemented using a trusted lock bit, which can be set to disable writes to a protected set of registers or address regions. The lock protection is intended to prevent modification of certain system configuration (e.g., memory/memory protection unit configuration).
However, if the lock bit does not effectively write-protect all system registers or controls that could modify the protected system configuration, then an adversary may be able to use software to access the registers/controls and modify the protected hardware configuration.
|
[
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Architecture"
},
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": "Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.",
"Phase": "Architecture and Design"
},
{
"Note": "Such issues could be introduced during implementation and identified later during Testing or System Configuration phases.",
"Phase": "Implementation"
}
] |
[
{
"Impact": [
"Modify Memory"
],
"Likelihood": null,
"Note": "System Configuration protected by the lock bit can be modified even when the lock is set.",
"Scope": [
"Access Control"
]
}
] |
[
{
"Description": "\n\n - Security lock bit protections must be reviewed for design inconsistency and common weaknesses.\n\n - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.\n\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design",
"Implementation",
"Testing"
],
"Strategy": null
}
] |
[
{
"Description": "Certain servers leave a write protection lock bit unset after boot, potentially allowing modification of parts of flash memory.",
"Link": "https://www.cve.org/CVERecord?id=CVE-2018-9085",
"Reference": "CVE-2018-9085"
},
{
"Description": "Chain: chipset has a race condition (CWE-362) between when an interrupt handler detects an attempt to write-enable the BIOS (in violation of the lock bit), and when the handler resets the write-enable bit back to 0, allowing attackers to issue BIOS writes during the timing window [REF-1237].",
"Link": "https://www.cve.org/CVERecord?id=CVE-2014-8273",
"Reference": "CVE-2014-8273"
}
] | null | null |
[
"176",
"680"
] |
[
{
"Authors": [
"CERT Coordination Center"
],
"Edition": null,
"ExternalReferenceID": "REF-1237",
"Publication": null,
"PublicationDay": "05",
"PublicationMonth": "01",
"PublicationYear": "2015",
"Publisher": null,
"Section": null,
"Title": "Intel BIOS locking mechanism contains race condition that enables write protection bypass",
"URL": "https://www.kb.cert.org/vuls/id/766164/",
"URLDate": null
}
] | null |
[
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"ModificationComment": null,
"ModificationDate": null,
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"ModificationReleaseDate": null,
"ModificationVersion": null,
"PreviousEntryName": null,
"SubmissionComment": null,
"SubmissionDate": "2020-01-15",
"SubmissionName": "Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi",
"SubmissionOrganization": "Intel Corporation",
"SubmissionReleaseDate": "2020-02-24",
"SubmissionVersion": "4.0",
"Type": "Submission",
"Version": null
},
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"ModificationComment": "updated Related_Attack_Patterns",
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"ModificationOrganization": "MITRE",
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"ModificationComment": "updated Maintenance_Notes",
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"ContributionComment": "reviewed content changes",
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"Type": "Rename",
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}
] |
Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
},
{
"CweID": "667",
"Nature": "ChildOf",
"Ordinal": null,
"ViewID": "1000"
}
] |
[
{
"Description": null,
"Ordinality": "Primary"
}
] |
[
{
"Description": "Set the lock bit. Attempt to modify the information protected by the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.",
"DetectionMethodID": null,
"Effectiveness": "High",
"EffectivenessNotes": null,
"Method": "Manual Analysis"
}
] |
[
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by the firmware.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "| Register | Field description | \n| --- | --- |\n| CRITICAL_TEMP_LIMIT | [31:8] Reserved field; Read only; Default 0 [7:0] Critical temp 0-255 Centigrade; Read-write-lock; Default 125 |\n| TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. A slope value used to map sensor reading to a degree Centigrade. Read-write; Default 25 |\n| TEMP_SENSOR_LOCK | [31:1] Reserved field; Read only; Default 0 [0] Lock bit, locks CRITICAL_TEMP_LIMIT register; Write-1-once; Default 0 |\n| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on a critical temperature detection; Read-write; Default 0 |\n| CURRENT_TEMP | [31:8] Reserved field; Read only; Default 0 [7:0] Current Temp 0-255 Centigrade; Read-only; Default 0 |",
"IntroText": null,
"Language": "Other",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "In this example note that only the CRITICAL_TEMP_LIMIT register is protected by the TEMP_SENSOR_LOCK bit, while the security design intent is to protect any modification of the critical temperature detection and response. \n\n\nThe response of the system, if the system heats to a critical temperature, is controlled by TEMP_HW_SHUTDOWN bit [1], which is not lockable. Also, the TEMP_SENSOR_CALIB register is not protected by the lock bit. \n\n\nBy modifying the temperature sensor calibration, the conversion of the sensor data to a degree centigrade can be changed, such that the current temperature will never be detected to exceed critical temperature value programmed by the protected lock. \n\n\nSimilarly, by modifying the TEMP_HW_SHUTDOWN.Enable bit, the system response detection of the current temperature exceeding critical temperature can be disabled.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "Change TEMP_HW_SHUTDOWN and TEMP_SENSOR_CALIB controls to be locked by TEMP_SENSOR_LOCK. \n\n| | \n|\n| TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. A slope value used to map sensor reading to a degree Centigrade. Read-write-Lock; Default 25; Locked by TEMP_SENSOR_LOCK bit[0] |\n| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on critical temperature detection; Read-write-Lock; Default 0; Locked by TEMP_SENSOR_LOCK bit[0] |",
"IntroText": null,
"Language": null,
"Nature": "Good",
"Reference": null
}
],
"ID": null
}
] | null | null | null | null | 3
|
[
[
"284",
"1233"
],
[
"664",
"662",
"667",
"1233"
],
[
"691",
"662",
"667",
"1233"
]
] |
[] |
1242
|
Inclusion of Undocumented Features or Chicken Bits
|
Base
|
Simple
|
Incomplete
|
The device includes chicken bits or undocumented features that can create entry points for unauthorized actors.
|
A common design practice is to use undocumented bits on a device that can be used to disable certain functional security features. These bits are commonly referred to as "chicken bits". They can facilitate quick identification and isolation of faulty components, features that negatively affect performance, or features that do not provide the required controllability for debug and test. Another way to achieve this is through implementation of undocumented features. An attacker might exploit these interfaces for unauthorized access.
|
[
{
"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Architecture"
},
{
"Class": "Not Technology-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": "ICS/OT",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": null,
"Phase": "Implementation"
},
{
"Note": null,
"Phase": "Documentation"
}
] |
[
{
"Impact": [
"Modify Memory",
"Read Memory",
"Execute Unauthorized Code or Commands",
"Gain Privileges or Assume Identity",
"Bypass Protection Mechanism"
],
"Likelihood": null,
"Note": null,
"Scope": [
"Confidentiality",
"Integrity",
"Availability",
"Access Control"
]
}
] |
[
{
"Description": "\n\nThe implementation of chicken bits in a released product is highly discouraged. If implemented at all, ensure that they are disabled in production devices. All interfaces to a device should be documented.\n",
"Effectiveness": "High",
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design",
"Implementation"
],
"Strategy": null
}
] | null | null |
[
{
"EntryID": "Part 4-1",
"EntryName": "Req SD-4",
"MappingFit": null,
"TaxonomyName": "ISA/IEC 62443"
},
{
"EntryID": "Part 4-1",
"EntryName": "Req SVV-3",
"MappingFit": null,
"TaxonomyName": "ISA/IEC 62443"
},
{
"EntryID": "Part 4-2",
"EntryName": "Req CR 2.12",
"MappingFit": null,
"TaxonomyName": "ISA/IEC 62443"
}
] |
[
"212",
"36"
] |
[
{
"Authors": [
"Ali Abbasi",
"Tobias Scharnowski",
"Thorsten Holz"
],
"Edition": null,
"ExternalReferenceID": "REF-1071",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": null,
"Publisher": null,
"Section": null,
"Title": "Doors of Durin: The Veiled Gate to Siemens S7 Silicon",
"URL": "https://i.blackhat.com/eu-19/Wednesday/eu-19-Abbasi-Doors-Of-Durin-The-Veiled-Gate-To-Siemens-S7-Silicon.pdf",
"URLDate": null
},
{
"Authors": [
"Sergei Skorobogatov",
"Christopher Woods"
],
"Edition": null,
"ExternalReferenceID": "REF-1072",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": null,
"Publisher": null,
"Section": null,
"Title": "Breakthrough Silicon Scanning Discovers Backdoor in Military Chip",
"URL": "https://www.cl.cam.ac.uk/~sps32/Silicon_scan_draft.pdf",
"URLDate": null
},
{
"Authors": [
"Chris Domas"
],
"Edition": null,
"ExternalReferenceID": "REF-1073",
"Publication": null,
"PublicationDay": null,
"PublicationMonth": null,
"PublicationYear": null,
"Publisher": null,
"Section": null,
"Title": "God Mode Unlocked: Hardware Backdoors in x86 CPUs",
"URL": "https://i.blackhat.com/us-18/Thu-August-9/us-18-Domas-God-Mode-Unlocked-Hardware-Backdoors-In-x86-CPUs.pdf",
"URLDate": null
},
{
"Authors": [
"Jonathan Brossard"
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Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null |
[
{
"Entries": [
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"IntroText": "Consider a device that comes with various security measures, such as secure boot. The secure-boot process performs firmware-integrity verification at boot time, and this code is stored in a separate SPI-flash device. However, this code contains undocumented \"special access features\" intended to be used only for performing failure analysis and intended to only be unlocked by the device designer.",
"Language": null,
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},
{
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"IntroText": null,
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"Nature": "Bad",
"Reference": null
},
{
"BodyText": "Remove all chicken bits and hidden features that are exposed to attackers. Add authorization schemes that rely on cryptographic primitives to access any features that the manufacturer does not want to expose. Clearly document all interfaces.",
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}
],
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}
] | null | null | null | null | 1
|
[
[
"284",
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]
] |
[] |
1252
|
CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
|
Base
|
Simple
|
Incomplete
|
The CPU is not configured to provide hardware support for exclusivity of write and execute operations on memory. This allows an attacker to execute data from all of memory.
|
CPUs provide a special bit that supports exclusivity of write and execute operations. This bit is used to segregate areas of memory to either mark them as code (instructions, which can be executed) or data (which should not be executed). In this way, if a user can write to a region of memory, the user cannot execute from that region and vice versa. This exclusivity provided by special hardware bit is leveraged by the operating system to protect executable space. While this bit is available in most modern processors by default, in some CPUs the exclusivity is implemented via a memory-protection unit (MPU) and memory-management unit (MMU) in which memory regions can be carved out with exact read, write, and execute permissions. However, if the CPU does not have an MMU/MPU, then there is no write exclusivity. Without configuring exclusivity of operations via segregated areas of memory, an attacker may be able to inject malicious code onto memory and later execute it.
|
[
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"Type": "Language"
},
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"Name": null,
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"Type": "Operating_System"
},
{
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"Name": null,
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"Type": "Architecture"
},
{
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},
{
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[
{
"Description": "\n\nImplement a dedicated bit that can be leveraged by the Operating System to mark data areas as non-executable. If such a bit is not available in the CPU, implement MMU/MPU (memory management unit / memory protection unit).\n",
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"Description": "\n\nIf MMU/MPU are not available, then the firewalls need to be implemented in the SoC interconnect to mimic the write-exclusivity operation.\n",
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}
] | null | null | null |
[
"679"
] |
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Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
"Nature": "ChildOf",
"Ordinal": "Primary",
"ViewID": "1000"
}
] | null | null |
[
{
"Entries": [
{
"BodyText": null,
"ExampleCode": null,
"IntroText": "MCS51 Microcontroller (based on 8051) does not have a special bit to support write exclusivity. It also does not have an MMU/MPU support. The Cortex-M CPU has an optional MPU that supports up to 8 regions.",
"Language": null,
"Nature": null,
"Reference": null
},
{
"BodyText": null,
"ExampleCode": "```\n\tThe optional MPU is not configured.\n```",
"IntroText": null,
"Language": "Other",
"Nature": "Bad",
"Reference": null
},
{
"BodyText": "If the MPU is not configured, then an attacker will be able to inject malicious data into memory and execute it.",
"ExampleCode": null,
"IntroText": null,
"Language": null,
"Nature": null,
"Reference": null
}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1252"
]
] |
[] |
1257
|
Improper Access Control Applied to Mirrored or Aliased Memory Regions
|
Base
|
Simple
|
Incomplete
|
Aliased or mirrored memory regions in hardware designs may have inconsistent read/write permissions enforced by the hardware. A possible result is that an untrusted agent is blocked from accessing a memory region but is not blocked from accessing the corresponding aliased memory region.
|
Hardware product designs often need to implement memory protection features that enable privileged software to define isolated memory regions and access control (read/write) policies. Isolated memory regions can be defined on different memory spaces in a design (e.g. system physical address, virtual address, memory mapped IO).
Each memory cell should be mapped and assigned a system address that the core software can use to read/write to that memory. It is possible to map the same memory cell to multiple system addresses such that read/write to any of the aliased system addresses would be decoded to the same memory cell.
This is commonly done in hardware designs for redundancy and simplifying address decoding logic. If one of the memory regions is corrupted or faulty, then that hardware can switch to using the data in the mirrored memory region. Memory aliases can also be created in the system address map if the address decoder unit ignores higher order address bits when mapping a smaller address region into the full system address.
A common security weakness that can exist in such memory mapping is that aliased memory regions could have different read/write access protections enforced by the hardware such that an untrusted agent is blocked from accessing a memory address but is not blocked from accessing the corresponding aliased memory address. Such inconsistency can then be used to bypass the access protection of the primary memory block and read or modify the protected memory.
An untrusted agent could also possibly create memory aliases in the system address map for malicious purposes if it is able to change the mapping of an address region or modify memory region sizes.
|
[
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"Class": "Not Language-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Language"
},
{
"Class": "Not OS-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Operating_System"
},
{
"Class": "Not Architecture-Specific",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Architecture"
},
{
"Class": null,
"Name": "Memory Hardware",
"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": null,
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"Prevalence": "Undetermined",
"Type": "Technology"
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{
"Class": null,
"Name": "Microcontroller Hardware",
"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": null,
"Name": "Network on Chip Hardware",
"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": "System on Chip",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
}
] | null |
[
{
"Note": null,
"Phase": "Architecture and Design"
},
{
"Note": null,
"Phase": "Implementation"
}
] |
[
{
"Impact": [
"Read Memory"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality"
]
},
{
"Impact": [
"Modify Memory"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Integrity"
]
},
{
"Impact": [
"DoS: Instability"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Availability"
]
}
] |
[
{
"Description": "The checks should be applied for consistency access rights between primary memory regions and any mirrored or aliased memory regions. If different memory protection units (MPU) are protecting the aliased regions, their protected range definitions and policies should be synchronized.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
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"Implementation"
],
"Strategy": null
},
{
"Description": "The controls that allow enabling memory aliases or changing the size of mapped memory regions should only be programmable by trusted software components.",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design",
"Implementation"
],
"Strategy": null
}
] | null | null | null |
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Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
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[
{
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[
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] |
[] |
1259
|
Improper Restriction of Security Token Assignment
|
Base
|
Simple
|
Incomplete
|
The System-On-A-Chip (SoC) implements a Security Token mechanism to differentiate what actions are allowed or disallowed when a transaction originates from an entity. However, the Security Tokens are improperly protected.
|
Systems-On-A-Chip (Integrated circuits and hardware engines) implement Security Tokens to differentiate and identify which actions originated from which agent. These actions may be one of the directives: 'read', 'write', 'program', 'reset', 'fetch', 'compute', etc. Security Tokens are assigned to every agent in the System that is capable of generating an action or receiving an action from another agent. Multiple Security Tokens may be assigned to an agent and may be unique based on the agent's trust level or allowed privileges. Since the Security Tokens are integral for the maintenance of security in an SoC, they need to be protected properly. A common weakness afflicting Security Tokens is improperly restricting the assignment to trusted components. Consequently, an improperly protected Security Token may be able to be programmed by a malicious agent (i.e., the Security Token is mutable) to spoof the action as if it originated from a trusted agent.
|
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"Prevalence": "Undetermined",
"Type": "Technology"
},
{
"Class": "System on Chip",
"Name": null,
"Prevalence": "Undetermined",
"Type": "Technology"
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"Note": null,
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[
{
"Impact": [
"Modify Files or Directories",
"Execute Unauthorized Code or Commands",
"Bypass Protection Mechanism",
"Gain Privileges or Assume Identity",
"Modify Memory",
"Modify Memory",
"DoS: Crash, Exit, or Restart"
],
"Likelihood": [
"High"
],
"Note": null,
"Scope": [
"Confidentiality",
"Integrity",
"Availability",
"Access Control"
]
}
] |
[
{
"Description": "\n\n - Security Token assignment review checks for design inconsistency and common weaknesses.\n\n - Security-Token definition and programming flow is tested in both pre-silicon and post-silicon testing.\n\n",
"Effectiveness": null,
"EffectivenessNotes": null,
"MitigationID": null,
"Phase": [
"Architecture and Design",
"Implementation"
],
"Strategy": null
}
] | null | null | null |
[
"121",
"681"
] | null |
[
{
"Note": "This entry is still under development and will continue to see updates and content improvements. Currently it is expressed as a general absence of a protection mechanism as opposed to a specific mistake, and the entry's name and description could be interpreted as applying to software.",
"Type": "Maintenance"
}
] |
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Allowed
|
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
|
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
|
[
"Acceptable-Use"
] | null |
[
{
"CweID": "284",
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}
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[
{
"Entries": [
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"BodyText": null,
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"IntroText": "For example, consider a system with a register for storing an AES key for encryption and decryption. The key is of 128 bits implemented as a set of four 32-bit registers. The key register assets have an associated control register, AES_KEY_ACCESS_POLICY, which provides the necessary access controls. This access-policy register defines which agents may engage in a transaction, and the type of transaction, with the AES-key registers. Each bit in this 32-bit register defines a security Token. There could be a maximum of 32 security Tokens that are allowed access to the AES-key registers. The number of the bit when set (i.e., \"1\") allows respective action from an agent whose identity matches the number of the bit and, if \"0\" (i.e., Clear), disallows the respective action to that corresponding agent.",
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"BodyText": "Let's assume the system has two agents: a Main-controller and an Aux-controller. The respective Security Tokens are \"1\" and \"2\". \n| Register | Description | Default | \n| --- | --- | --- |\n| AES_ENC_DEC_KEY_0 | AES key [0:31] for encryption or decryption | 0x00000000 |\n| AES_ENC_DEC_KEY_1 | AES key [32:63] for encryption or decryption | 0x00000000 |\n| AES_ENC_DEC_KEY_2 | AES key [64:95] for encryption or decryption | 0x00000000 |\n| AES_ENC_DEC_KEY_3 | AES key [96:127] for encryption or decryption | 0x00000000 |\n| AES_KEY_ACCESS_POLICY | AES key access register [31:0] | 0x00000002 |",
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},
{
"BodyText": "An agent with Security Token \"1\" has access to AES_ENC_DEC_KEY_0 through AES_ENC_DEC_KEY_3 registers. As per the above access policy, the AES-Key-access policy allows access to the AES-key registers if the security Token is \"1\".",
"ExampleCode": null,
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},
{
"BodyText": null,
"ExampleCode": "The Aux-controller could program its Security Token to \"1\" from \"2\".",
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"Language": "Other",
"Nature": "Bad",
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},
{
"BodyText": "The SoC does not properly protect the Security Token of the agents, and, hence, the Aux-controller in the above example can spoof the transaction (i.e., send the transaction as if it is coming from the Main-controller to access the AES-Key registers)",
"ExampleCode": null,
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},
{
"BodyText": null,
"ExampleCode": "The SoC needs to protect the Security Tokens. None of the agents in the SoC should have the ability to change the Security Token.",
"IntroText": null,
"Language": "Other",
"Nature": "Good",
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}
],
"ID": null
}
] | null | null | null | null | 1
|
[
[
"284",
"1259"
]
] |
[] |
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